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ADCDS-1405
14-Bit, 5 Megapixels/Second Imaging Signal Processor
FEATURES
* * * * * * * * * * 14-bit resolution 5MPPS throughput rate (14-bits) Functionally complete Very low noise Excellent Signal-to-Noise ratio Edge triggered Small, 40-pin, TDIP package Low power, 700mW typical Low cost Programmable Analog Bandwidth
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INPUT/OUTPUT CONNECTIONS
FUNCTION FINE GAIN ADJUST OFFSET ADJUST DIRECT INPUT INVERTING INPUT NON-INVERTING INPUT +2.4V REF. OUTPUT ANALOG GROUND NO CONNECT NO CONNECT BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION NO CONNECT +12V -5VA ANALOG GROUND +5VA ANALOG GROUND +5VD DIGITAL GROUND DIGITAL GROUND A1 A NO CONNECT NO CONNECT DATA VALID REFERENCE HOLD START CONVERT OUT-OF-RANGE BIT 1 (MSB) BIT 2 BIT 3
GENERAL DESCRIPTION
The ADCDS-1405 is an application-specific video signal processor designed for electronic-imaging applications that employ CCD's (charge coupled devices) as their photodetector. The ADCDS-1405 incorporates a "user configurable" input amplifier, a CDS (correlated double sampler) and a sampling A/D converter in a single package, providing the user with a complete, high performance, lowcost, low-power, integrated solution. The key to the ADCDS-1405's performance is a unique, highspeed, high-accuracy CDS circuit, which eliminates the effects of residual charge, charge injection and "kT/C" noise on the CCD's output floating capacitor, producing a "valid video" output signal. The ADCDS-1405 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling A/D converter. The ADCDS-1405 requires only the rising edge of start convert pulse to initiate its conversion process. Additional features of the ADCDS-1405 include gain adjust, offset adjust, precision +2.4V reference, and a programmable analog bandwidth function.
+12VA 39 759 INVERTING INPUT 4 5239
-5VA 38
+5VA 36
+5VD 34
INPUT AMPLIFIER 0.01F DIRECT INPUT 3 NON-INVERTING INPUT 5 5K 9 CORRELATED DOUBLE SAMPLER
25 START CONVERT 1 FINE GAIN ADJUST
23 BIT 1 (MSB) SAMPLING A/D 10 BIT 14 (LSB)
OFFSET ADJUST 2
REFERENCE HOLD 26
TIMING AND CONTROL
24 OUT-OF-RANGE 6 +2.4V REFERENCE OUTPUT
32, 33 DIGITAL GROUND
27 DATA VALID
30 31 AO A1
7, 35, 37 ANALOG GROUND
Figure 1. ADCDS-1405 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 * Email: sales@datel.com * Internet: www.datel.com
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ABSOLUTE MAXIMUM RATINGS
PARAMETERS +12V Supply (Pin 32) -5V Supply (Pin 31) +5V Supply (Pin 28, 29) Digital Input (Pin 23, 24) Analog Input (Pin 3,4,5) Lead Temperature (10 seconds) MIN. 0 -0.3 0 -0.3 -5 -- TYP. -- -- -- -- -- -- MAX. +14 +6.5 -6.5 Vdd+0.3V +5 300 UNITS Volts Volts Volts Volts Volts C DYNAMIC PERFORMANCE Reference Hold Aquisition Time Droop @ +25C @ -55 to +125C Peak Harmonic (SFDR) (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Peak Harmonic (SFDR) (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Total Harmonic Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Signal-to-Noise Ratio Without Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Signal-to-Noise Ratio With Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C SIGNAL TIMING Conversion Rate -55 to +125C Conversion Time Start Convert Pulse Width POWER REQUIREMENTS Power Supply Range +12V Supply +5V Supply -5V Supply 5 -- 20 -- 200 150 -- -- -- MSPS nsec nsec MIN. 70 -- -- TYP. -- 25 100 MAX. -- -- -- UNITS ns mV/us mV/us
FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range, under the following conditions:
Vcc=+12V, +Vdd=+5V, Vee=-5V, fin=98KHz, sample rate=5MSPS.
-- -- --
-76 -76 -74
-- -- --
dB dB dB
ANALOG INPUT Input Voltage Range (externally configurable) Input Resistance Input Capacitance DIGITAL INPUTS Logic Levels Logic 1 Logic 0 Logic Loading Logic 1 Logic 0 DIGITAL OUTPUTS Logic Levels Logic 1 (IOH = .5ma) Logic 1 (IOH = 50a) Logic 0 (IOL = 1.6ma) Logic 0 (IOL = 50ua) Internal Reference Voltage (Fine gain adjust pin (1) grounded) +25C 0 to 70C -55 to +125C External Current STATIC PERFORMANCE Differential Nonlinearity (Histogram, 98kHz) +25C 0 to 70C -55 to +125C Integral Nonlinearity +25C 0 to 70C -55 to +125C Guaranteed No Missing Codes 0 to 70C -55 to +125C DC Noise +25C 0 to 70C -55 to +125C Offset Error +25C 0 to 70C -55 to +125C Gain Error +25C 0 to 70C -55 to +125C
MIN. 0.350 -- --
TYP. 2.8 5000 10
MAX. -- -- --
UNITS Volts p-p Ohm pF
-- -- --
-76 -76 -74
-- -- --
dB dB dB
+3.5 -- -- --
-- -- -- --
-- +.80 +10 -10
Volts Volts uA uA
-- -- --
-75 -75 -74
-- -- --
dB dB dB
-- -- --
-76 -76 -74
-- -- --
dB dB dB
+2.4 +4.5 -- --
-- -- -- --
-- -- +0.4 +0.1
Volts Volts Volts Volts
73 73 70
75 75 73
-- -- --
dB dB dB
2.35 2.35 2.35 --
2.4 2.4 2.4 1.0
2.45 2.45 2.45 --
Volts Volts Volts mA
73 73 70
75 75 73
-- -- --
dB dB dB
-0.90 -0.90 -1.0 -- -- -- 14 14 -- -- -- -- -- -- -- -- --
0.5 0.5 0.6 2.5 2.5 2.5 -- -- 0.85 1.0 1.25 0.6 0.6 0.6 1.00 1.35 1.35
+.90 +.90 +1.0 -- -- -- -- -- -- -- -- 1.25 1.25 1.45 2.8 2.8 2.8
LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB %FSR %FSR %FSR %FSR %FSR %FSR
-- -- --
71 71 70
-- -- --
dB dB dB
-- -- --
71 71 70
-- -- --
dB dB dB
+11.4 +4.75 -4.75
+12.0 +5.0 -5.0
+12.6 +5.25 -5.25
Volts Volts Volts
2
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ADCDS-1405
initial offset and gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2) features. Direct Mode (AC Coupled)
-- -- -- -- +50 -40 0.7 0.02 +56 -45 0.9 0.03 mA mA Watts
%FSR/%V
POWER REQUIREMENTS Power Supply Current +12V Supply Power Supply Current +5V Supply -5V Supply Power Dissipation Power Supply Rejection (5%) @ +25C ENVIRONMENTAL Operating Temperature Range ADCDS-1405 ADCDS-1405EX Storage Temperature Package Type Weight
MIN.
TYP.
MAX.
UNITS
--
+20
+26
mA
This is the most common input configuration as it allows the ADCDS-1405 to interface directly to the output of the CCD with a minimum amount of analog "front-end" circuitry. This mode of operation is used with full-scale video input signals from 0.350Vp-p to 2.8Vp-p. Figure 2a. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. The coarse gain of the input amplifier is determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1% tolerance. Additional fine gain adjustment can be accomplished using the Fine Gain Adjust (pin 1 see Figure 5). Figure 2b. describes the typical configuration for applications using a video input signal with an amplitude greater than 0.350Vp-p and less than 2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS1405 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the input amplifier can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance.
4 759 5239
0 -55 -65
-- -- --
+70 +125 +150
C C C
40-pin, TDIP 16.10 grams
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADCDS-1405 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital grounds are connected to each other internally. Depending on the level of digital switching noise in the overall CCD system, the performance of the ADCDS-1405 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. The use of a single +5V analog supply for both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial. 2. Bypass all power supplies to ground with a 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor. Locate the capacitors as close to the package as possible. 3. If using the suggested offset and gain adjust circuits (Figure 3 & 5), place them as close to the ADCDS-1405's package as possible. 4. A0 and A1 (pins 30, 31) should be bypassed with 0.1f capacitors to ground to reduce susceptibility to noise. ADCDS-1405 Modes of Operation The input amplifier stage of the ADCDS-1405 provides the designer with a tremendous amount of flexibility. The architecture of the ADCDS-1405 allows its input-amplifier to be configured in any of the following configurations: * Direct Mode (AC coupled) * Non-Inverting Mode * Inverting Mode When applying inputs which are less than 2.8Vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8Vp-p signal at the inputamplifier's output (Vout). In all three modes of operation, the video portion of the signal at the CDS input (i.e. input-amplifier's Vout) must be more negative than its associated reference level and Vout should not exceed 2.8V DC. The ADCDS-1405 achieves it specified accuracies without the need for external calibration. If required, the device's small
VIN NO CONNECT
3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2a.
Rext 4 759 5239
VIN NO CONNECT
3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2b.
Rext 759 5239
4
NO CONNECT VIN
3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2c.
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Non-Inverting Mode The non-inverting mode of the ADCDS-1405 allows the designer to either attenuate or add non-inverting gain to the video input signal. This configuration also allows bypassing the ADCDS-1405's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. Figure 2c. describes the typical configuration for applications using video input signals with amplitudes greater than 0.350Vp-p and less than 2.8Vp-p (with common mode limit of 2.5V DC). Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1405 can be set with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the circuit can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance. Figure 2d. describes the typical configuration for applications using a video input signal whose amplitude is greater than 2.8Vp-p. Using a single external series resistor (Rext 1) in conjunction with the internal 5K (1%) resistor to ground, an attenuation of the input signal can be achieved. Additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]* [1+(523/(75+Rext2))], with all internal resistors having a 1% tolerance.
Rext2
Inverting Mode The inverting mode of operation can be used in applications where the analog input to the ADCDS-1405 has a video input signal whose amplitude is more positive than its associated reference level. The ADCDS-1405s correlated double sampler (i.e. input amplifier's VOUT) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). Using the ADCDS-1405 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have occurred prior to the ADCDS-1405. Figure 2e. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. Additional fine gain adjustments can be made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = -VIN*(523/75), with all internal resistors having a 1% tolerance. Figure 2f. describes the typical configuration used in applications needing to invert video input signals whose amplitude is greater than 0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial gain of the ADCDS1405 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = -VIN*(523/75+Rext), with all internal resistors having a 1% tolerance.
A D C D S -1 4 0 5
3 0.01F VOUT = 2.8Vp-p
4
759
5239
NO CONNECT Rext1 VIN 5 5k9
+5V 20K9
E x te rn a l S e r ie s R e s is to r
O ffs e t A d ju s t 2
Figure 2d.
759 5239
5V
-VIN
4
3 NO CONNECT 5
0.01f VOUT = 2.8Vp-p
Figure 3. Offset Adjustment Circuit
5k9
C o a r s e G a in A d ju s tm e n t P lo t E x te r n a l G a in R e s is to r v s . F u ll S c a le V id e o In p u t
E x te r n a l G a in R e s is to r (O h m s )
10000
D ir e c t M o d e & N o n - In v e r tin g M ode In v e r tin g M o d e
Figure 2e.
Rext -VIN 4 759 5239
1000
3 NO CONNECT 5
0.01f VOUT = 2.8Vp-p
100
5k9
10
0 .2 5
0 .5
0 .7 5
1
1 .2 5
1 .5
1 .7 5
2
2 .2 5
2 .5
2 .7 5
3
F u ll S c a le V id e o S ig n a l (V o lts )
Figure 2f.
Figure 4. Coarse Gain Adjustment Plot
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Offset Adjustment Manual offset adjustment for the ADCDS-1405 can be accomplished using the adjustment circuit shown in Figure 3. A software controlled D/A converter can be substituted for the 20K potentiometer. The offset adjustment feature allows the user to adjust the Offset/Dark Current level of the ADCDS-1405 until the output bits are 00 0000 0000 0000 and the LSB flickers between 0 and 1. Offset adjust should be performed before gain adjust to avoid interaction. The ADCDS-1405's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing 5V supplies. Offset Adjustment Sensitivity It should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the ADCDS-1405 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer.
A D C D S -1 4 0 5 +5V 20K9 F in e G a in A d ju s t 1
For Example: External 50K resistor: 1. 10mV of noise or voltage variation at the potentiometer will produce 0.25LSB's of output variation. 2. 100mV of noise or voltage variation at the potentiometer will produce 2.5LSB's of output variation. The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. If a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. The ADCDS-1405's +2.4V reference output could be configured to provide the reference voltage for this type of application. Fine Gain Adjustment Fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (Rext) and/ or the unavailability of exact coarse gain resistor (Rext) values. Note, the fine gain adjustment will not change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead, the gain of the ADCDS-1405's internal A/D is adjusted allowing the actual input amplifier's full scale VOUT to produce an output code of all ones (11 1111 1111 1111). Fine gain adjustment for the ADCDS-1405 is accomplished using the adjustment circuit shown below (Figure 5). A software controlled D/A converter can be substituted for the 20K potentiometer. The fine gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired Full Scale digital output of 11 1111 1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust should be performed following the offset adjust
5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment vs. External Series Resistor 10000
LSB's of Adjustment
Output Variation (LSB's)
Offset Adjustment Sensitivity External Series Resistor vs. Output Variation (LSB's) 100 Peak-Peak variation at potentiometer 100mV
1000
10
1
100
0.1
10mV
10
0.01
1mV
0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
55k 60k
External Series Resistor (Ohm's)
External Series Resistor Value (Ohms)
Figure 6. Offset Adjustment vs. External Series Resistor
Figure 7. Offset Adjustment Sensitivity
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to avoid interaction. The fine gain adjust provides 256 codes of adjust when 5V supplies are used for the Fine Gain Adjust Circuit. Out-of-Range Indicator The ADCDS-1405 provides a digital Out-of-Range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal A/D converter. The digital output bits and the Out-of-Range signal correspond to a particular sampled video input voltage, with both of these signals having a common pipeline delay. Using the circuit described in Figure 8., both overrange and underrange conditions can be detected (see Table 1). When combined with a D/A converter, digital detection and orrection can be performed for both the gain and offset errors. Output Coding The ADCDS-1405's output coding is Straight Binary as indicated in Table 2. The table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding video signal voltage. (These voltages are referred to the output of the ADCDS-1405's input amplifier's VOUT). Programmable Analog Bandwidth Function When interfacing to CCD arrays with very high-speed "readout" rates, the ADCDS-1405's input stage must have sufficient analog bandwidth to accurately reproduce the output signals of the CCD array. The amount of analog bandwidth determines how quickly and accurately the "Reference Hold" and the "CDS output" signals will settle. If only a single analog bandwidth was offered, the ADCDS-1405's bandwidth would be set to acquire and digitize CCD output signals to 14-bit accuracy, at maximum conversion rate of 5MHz (200ns see Figure 11. for details). Applications not requiring the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance. The ADCDS-1405 avoids this situation by offering a fully programmable analog bandwidth function. The ADCDS-1405 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise performance (DC noise of 0.3 LSBs rms possible) for the application being considered. Table 3. describes how to select the appropriate reference hold "aquisition time" and CDS output "settling time" needed for a particular application. Each of the selections listed in Table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. Increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the ADCDS1405's output. The ADCDS-1405 uses a two bit digital word to select four different analog bandwidths for the ADCDS-1405's input stage (See Table 3. for details).
MSB "OVERRANGE" OUT-OF-RANGE "UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Table 1. Out-of-Range Conditions OUT OF RANGE 0 0 1 1 MSB 0 1 0 1 OVER RANGE 0 0 0 1 UNDER RANGE 0 0 1 0 INPUT SIGNAL In Range In Range Underrrange Overrange
Table 2. Output Coding INPUT AMPLIFIER VOUT, (VOLTS P-P) Video Signal-Reference Signal > -2.80000 -2.80000 -2.10000 -1.40000 -0.70000 -0.35000 -0.000171 0 <0 SCALE >Full Scale -1LSB Full Scale -1LSB 3/4FS 1/2FS 1/4FS 1/8FS 1 LSB 0 <0 DIGITAL OUTPUT 11 1111 1111 1111 11 1111 1111 1111 11 0000 0000 0000 10 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 OUT-OF-RANGE 1 0 0 0 0 0 0 0 1
Video Signal-Reference Signal
Notes:
Input Amplifier VOUT = (Video Signal - Reference Level) The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference
level and VOUT should not exceed 2.8V DC.
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Table 3. Programmable Analog Bandwidth REFERENCE HOLD "AQUISITION TIME" 70ns 100ns 200ns 450ns Note: See Figure 11. for timing details CDS OUTPUT "SETTLING TIME" 90ns 120ns 250ns 500ns A0 (Pin 30) 0 1 0 1 A1 (Pin 31) 0 0 1 1 ADCDS-1405 MAXIMUM CONVERSION RATE 5MHz 3MHz 2MHz 1MHz -3dB BW 10.5MHz 6.6MHz 3.7MHz 2.5MHz
+12V 4 .7 F +
+5VD 4 .7 F + +
5VA 4 .7 F
+5VA 4 .7 F +
0 .1 F +5V 1 20K9 5V +5V 20K9 3 5V 4 5 30 A A1 0 .1 F 0 .1 F 31 25 26 7,35,37 E x te r n a l S e r ie s R e s is to r 2 39 F IN E G A IN
0 .1 F 36 A D JU S T
0 .1 F 38
0 .1 F 36 23 22 21 20 B IT 1 (M S B ) B IT 2 B IT 3 B IT 4 B IT 5 B IT 6 B IT 7 B IT 8 B IT 9 B IT 1 0 B IT 1 1 B IT 1 2 B IT 1 3 B IT 1 4 (L S B )
O FFS E T A D JU S T D IR E C T IN P U T IN V E R T IN G IN P U T IN P U T
19 18 17 16 15 14 13 12 11 10
N O N -IN V E R T IN G
A D C D S -1 4 0 5
START CONVERT 6 R EF.H O LD AN ALO G GROUND
+ 2 .4 V R E F E R E N C E O U T 24 27 O U T -O F -R A N G E D A T A V A L ID D IG IT A L G R O U N D
32,33
Figure 9. ADCDS-1405 Connection Diagram
Timing The ADCDS-1405 requires two independently operated signals to accurately digitize the analog output signal from the CCD array. * * Reference Hold (pin 26) Start Convert (pin 25)
reference signal. The Reference Hold Signal allows the user to control the exact moment when the sample-hold is placed into the "hold" mode. For optimal performance the samplehold should be placed into the "hold" mode once the reference signal has fully settled from all switching transients to the desired accuracy (user defined). Once the reference signal has been "held" and the video portion of the CCD's analog output signal appears at the ADCDS-1405's input, the ADCDS-1405's correlated double sampler produces a "CDS Output" signal (see Figure 11.)
The "Reference Hold" signal controls the operation of an internal sample-hold circuit. A logic "1" places the samplehold into the hold mode, capturing the value of the CCD's
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which is the difference between the "held" reference level and its associated video level. When the "CDS Output" signal has settled to the desired accuracy (user defined), the A/D conversion process can be initiated with the rising edge of a single start convert (Pin 25) signal. Once the A/D conversion has been initiated, Reference Hold (Pin 26) can be placed back into the "Acquisition" mode in order to begin aquiring the next reference level. For optimal performance the ADCDS-1405's internal sample-hold should be placed back into the "Aquisition" mode (Reference Hold to logic "0") during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is defined as the period when the CCD's reference signal has settled from all switching transients to the desired accuracy (see Figure 10.)). Placing the sample-hold back into the "aquisition" mode during the "Reference Quiet Time" prevents the ADCDS-1405's internal amplifiers from unecessarily tracking (reproducing) the large switching transients that occur during the CCD's reset to reference transition.
R eset
R e fe re n c e " Q u ie t T im e " CCD OUTPUT R e fe re n c e
V id e o 1 0 0 N S M IN . REFERENCE H O LD H O LD A c q u is itio n m o d e d u r in g R e fe r e n c e " Q u ie t T im e " N o te : F o r o p tim a l p e r fo r m a n c e ( F a s te s t A c q u is itio n T im e ) , th e A D C D S - 1 4 0 5 s h o u ld b e p la c e d in to th e A c q u is itio n m o d e ( R e fe r e n c e H o ld to lo g ic " 0 " ) d u r in g t h e C C D o u t p u t 's R e f e r e n c e " Q u ie t T im e " . R e f e r e n c e " Q u ie t T im e " is d e f in e d a s t h e p e r io d w h e n t h e r e f e r e n c e s ig n a l's s w it c h in g t r a n s ie n t s h a v e s e ttle d to a n a c c e p ta b le ( u s e r d e fin e d ) a c c u r a c y .
A c q u is itio n T im e
Figure 10. Reference Hold Timing
R esetN
R esetN +1
R esetN +2
R esetN +3
R esetN +4
CCD OUTPUT
R e f.NN V id e o N
R e f. N + 1 V id e o N + 1
R e f. N + 2
V V i di d e e o o N N + + 2 1
R e f. N + 3 V V i di d e e o o N N + + 3 1
R e f. N + 4
12 30 30 n s m i n . R E F E R E N C E H O L D IN H o ld 17 25 0n ns s m m i n i .n s s e e t t tl i l n i n g g t li im n e
A c q u is itio n T im e 17 0 0n ns s m m i n i n. .
F u ll S c a le S te p CDS OUTPUT N N+1 5 0 n s ty p . N+2 N+3
START CONVERT
5 0 n s ty p .
N+1
N+2
N+3
D A T A V A L ID In v a lid d a ta DATA OUTPUT D A T A N -4 V A L ID
N -4
3 0 n s m in ., 5 0 n s m a x .
N -3
N -2
N -1
2 0 n s m ia n x D A T A N -3 V A L ID D A T A N -2 V A L ID D A T A N -1 V A L ID D A T A N V A L ID
Figure 11. ADCDS-1405 Timing Diagram
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MECHANICAL DIMENSIONS INCHES (mm)
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1 4 -B IT , 5 M H z IM A G IN G S IG N A L P R O C E S S O R
M a d e in U S A
A D C D S -1 4 0 5
1 .2 7 T Y P . (3 2 .2 5 )
2 .2 4 T Y P . (5 6 .9 0 )
0 .2 3 T Y P . (5 .8 4 )
0 .1 0 0 T Y P . (2 .5 4 0 ) 1 .9 0 0 0 .0 0 8 (4 8 .2 6 0 )
0 .9 0 0 0 .0 1 0 (2 2 .8 6 )
ORDERING INFORMATION
MODEL OPERATING TEMPERATURE RANGE 40-PIN PACKAGE
ADCDS-1405 ADCDS-1405EX
0 to 70C -55 to 125C
TDIP TDIP
(R)
(R)
ISO 9001
REGISTERED
DS-0503A
3/03
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

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